In a data processing system, store instructions store a single data operand from a register into a memory device. The source operand to be stored in the memory device may be dependent upon the execution of prior instructions for its calculation. Moreover, the store instruction may include address operands from which the target address in the memory device is to be calculated. That is, the location in the memory device for the storage of the source data operand is calculated from address operands specified in the store instruction.
Thus, the execution of a store instruction may depend both on the availability of a source operand and the generation of the store target address. Moreover, the generation of the target address may also depend on the availability of precursor source operands for the computation of the address. According to the prior art, the execution of a fixed-point store instruction is held until both address and data operands are available. Subsequent instructions which depend on the results of the fixed-point store instruction are then also delayed until the instruction upon which they depend completes. Floating-point store mechanisms according to the prior art are not so delayed.
The necessity for both address and data operand availability thus delays execution of dependent instructions subsequent to a fixed-point store operation. Thus, there is a need in the art for a mechanism by which address calculations are decoupled from the data portion of the store, thereby reducing the latency of the store instruction, and dependent instructions succeeding the store instruction. There is, additionally, a need for a store mechanism that is common for both fixed-point and floating-point operations.